This invention relates generally to semiconductor integrated circuits and more particularly, it relates to an improved sense amplifier circuit for use in high density random access memory devices to produce high speed, low noise operations.
As it generally known, sense amplifiers are used to detect small voltage differentials on pairs of bit lines which have a number of memory cells connected therebetween. In a cross-coupled pair sense amplifier, the amplifier feeds back to the bit lines. This is typically necessary to restore data in the selected storage or memory cell. The sense amplifier is generally expected to be able to detect differentials of approximately 200-400 millivolts on the bit lines. The amplifier senses the voltage differential on the bit lines and begins to further increase the voltage differential. In the usual practice, the bit lines are precharged and equalized in a precharge cycle by precharge transistors prior to activation of an access signal during a read or access cycle. Thus, it is necessary to delay assertion of a sense signal with respect to the access signal until after the bit lines have separated approximately 200-400 millivolts.
However, the delay in the assertion of the sense signal will create a corresponding delay in the deassertion of the sense signal, thereby causing it to overlap into the assertion of the next precharge cycle. As a result, a current spike in the range of 1-10 mA will be generated to a power supply terminal VSS since both the precharge transistors and the sense amp transistors will all be turned on. In a memory having a number of paired bit lines (columns), this could cause a current spike on the order of 1-2 amps so as to produce a ringing effect on the power supply terminal VSS.
It would therefore be desirable to provide an improved sense amplifier in which the sense nodes are isolated from the bit lines during the assertion of a sense signal in order to eliminate the occurrence of current spikes, but yet retain the gain in the cross-coupled sense amplifier. The sense nodes are capable of being quickly discharged without requiring large sense amp transistors since the bit line loading has been isolated.